Hard Real-time Scheduling for Parallel Run-time Systems

被引:2
|
作者
Dinda, Peter [1 ]
Wang, Xiaoyang [1 ]
Wang, Jinghang [1 ]
Beauchene, Chris [1 ]
Hetland, Conor [1 ]
机构
[1] Northwestern Univ, Evanston, IL 60208 USA
来源
HPDC '18: PROCEEDINGS OF THE 27TH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE PARALLEL AND DISTRIBUTED COMPUTING | 2018年
基金
美国能源部; 美国国家科学基金会;
关键词
hard real-time systems; parallel computing; HPC; IMPLEMENTATION;
D O I
10.1145/3208040.3208052
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
High performance parallel computing demands careful synchronization, timing, performance isolation and control, as well as the avoidance of OS and other types of noise. The employment of soft real-time systems toward these ends has already shown considerable promise, particularly for distributed memory machines. As processor core counts grow rapidly, a natural question is whether similar promise extends to the node. To address this question, we present the design, implementation, and performance evaluation of a hard real-time scheduler specifically for high performance parallel computing on shared memory nodes built on x64 processors, such as the Xeon Phi. Our scheduler is embedded in a kernel framework that is already specialized for high performance parallel run-times and applications, and that meets the basic requirements needed for a real-time OS (RTOS). The scheduler adds hard real-time threads both in their classic, individual form, and in a group form in which a group of parallel threads execute in near lock-step using only scalable, per-hardware-thread scheduling. On a current generation Intel Xeon Phi, the scheduler is able to handle timing constraints down to resolution of similar to 13,000 cycles (similar to 10 mu s), with synchronization to within similar to 4,000 cycles (similar to 3 mu s) among 255 parallel threads. The scheduler isolates a parallel group and is able to provide resource throttling with commensurate application performance. We also show that in some cases such fine-grain control over time allows us to eliminate barrier synchronization, leading to performance gains, particularly for fine-grain BSP workloads.
引用
收藏
页码:14 / 26
页数:13
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