Two-parallel Reed-Solomon based FEC architecture for optical communications

被引：18

作者：

Lee, Seungbeom ^{[1
]}

Choi, Chang-Seok ^{[1
]}

Lee, Hanho ^{[1
]}

机构：

[1] Inha Univ, Sch Informat & Commun Engn, Inchon 402751, South Korea

来源：

IEICE ELECTRONICS EXPRESS | 2008年 / 5卷 / 10期

关键词：

Reed-Solomon code; forward error correction; two-parallel;

D O I：

10.1587/elex.5.374

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a high-speed Forward Error Correction (FEC) architecture based on two-parallel Reed-Solomon (RS) decoder for 10 and 40-Gb/s optical communication systems. A highspeed two-parallel RS(255, 239) decoder has been proposed and the derived structure can also be applied to implement the 10 and 40-Gb/s RS FEC architectures. The implementation results show that 16-Ch. RS FEC architecture can operate at a clock frequency of 160MHz and has a throughput of 41 Gb/s for the Xilinx Virtex4 FPGA. Also, RS FEC operates at a clock frequency of 400MHz and has a throughput of 102 Gb/s for 0.18-mu m CMOS technology.

引用

页码：374 / 380

页数：7

共 5 条

[1] ITU-T, 2000, G975 ITUT
[2] High-speed VLSI architecture for parallel Reed-Solomon decoder
Lee, H
[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2003, 11 (02) : 288 - 294
[3] A high-speed pipelined degree-computationless modified euclidean algorithm architecture for Reed-Solomon decoders
Lee, Seungbeoin
Lee, Hanho
Shin, Jongyoon
Ko, Je-Soo
[J]. 2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 901 - +
[4] SHAO HM, 1985, IEEE T COMPUT, V34, P393, DOI 10.1109/TC.1985.1676579
[5] 10-and 40-Gb/s forward error correction devices for optical communications
Song, LL
Yu, ML
Shaffer, MS
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (11) : 1565 - 1573

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