DrawerPipe: A Reconfigurable Pipeline for Network Processing on FPGA-Based SmartNIC

被引:10
|
作者
Li, Junnan [1 ]
Sun, Zhigang [1 ]
Yan, Jinli [1 ]
Yang, Xiangrui [1 ]
Jiang, Yue [1 ]
Quan, Wei [1 ]
机构
[1] Natl Univ Def Technol, Coll Comp, Changsha 410073, Peoples R China
基金
中国国家自然科学基金;
关键词
network processing; FPGA; SmartNIC; reconfigurable pipeline; programmable module indexing; PACKET CLASSIFICATION;
D O I
10.3390/electronics9010059
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
In the public cloud, FPGA-based SmartNICs are widely deployed to accelerate network functions (NFs) for datacenter operators. We argue that with the trend of network as a service (NaaS) in the cloud is also meaningful to accelerate tenant NFs to meet performance requirements. However, in pursuit of high performance, existing work such as AccelNet is carefully designed to accelerate specific NFs for datacenter providers, which sacrifices the flexibility of rapidly deploying new NFs. For most tenants with limited hardware design ability, it is time-consuming to develop NFs from scratch due to the lack of a rapidly reconfigurable framework. In this paper, we present a reconfigurable network processing pipeline, i.e., DrawerPipe, which abstracts packet processing into multiple "drawers" connected by the same interface. NF developers can easily share existing modules with other NFs and simply load core application logic in the appropriate "drawer" to implement new NFs. Furthermore, we propose a programmable module indexing mechanism, namely PMI, which can connect "drawers" in any logical order, to perform distinct NFs for different tenants or flows. Finally, we implemented several highly reusable modules for low-level packet processing, and extended four example NFs (firewall, stateful firewall, load balancer, IDS) based on DrawerPipe. Our evaluation shows that DrawerPipe can easily offload customized packet processing to FPGA with high performance up to 100 Mpps and ultra-low latency (<10 mu s). Moreover, DrawerPipe enables modular development of NFs, which is suitable for rapid deployment of NFs. Compared with individual NF development, DrawerPipe reduces the line of code (LoC) of the four NFs above by 68%.
引用
收藏
页数:24
相关论文
共 50 条
  • [1] DrawerPipe: A Reconfigurable Packet Processing Pipeline for FPGA
    Li J.
    Yang X.
    Sun Z.
    Jisuanji Yanjiu yu Fazhan/Computer Research and Development, 2018, 55 (04): : 717 - 728
  • [2] High-Performance Reconfigurable Pipeline Implementation for FPGA-Based SmartNIC
    Song, Xiaoyong
    Lu, Rui
    Guo, Zhichuan
    MICROMACHINES, 2024, 15 (04)
  • [3] FACL: A Flexible and High-Performance ACL engine on FPGA-based SmartNIC
    Jia, Chengjun
    Li, Chenglong
    Li, Yifan
    Hu, Xiaohe
    Li, Jun
    2022 IFIP NETWORKING CONFERENCE (IFIP NETWORKING), 2022,
  • [4] FPGA-Based Dynamically Reconfigurable SQL Query Processing
    Ziener, Daniel
    Bauer, Florian
    Becher, Andreas
    Dennl, Christopher
    Meyer-Wegener, Klaus
    Schuerfeld, Ute
    Teich, Juergen
    Vogt, Joerg-Stephan
    Weber, Helmut
    ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, 2016, 9 (04)
  • [5] FPGA-based Garbling Accelerator with Parallel Pipeline Processing
    Oishi, Rin
    Kadomoto, Junichiro
    Irie, Hidetsugu
    Sakai, Shuichi
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2023, E106D (12) : 1988 - 1996
  • [6] Honeycomb: Ordered Key-Value Store Acceleration on an FPGA-Based SmartNIC
    Liu, Junyi
    Dragojevic, Aleksandar
    Fleming, Shane
    Katsarakis, Antonios
    Korolija, Dario
    Zablotchi, Igor
    Ng, Ho-Cheung
    Kalia, Anuj
    Castro, Miguel
    IEEE TRANSACTIONS ON COMPUTERS, 2024, 73 (03) : 857 - 871
  • [7] An FPGA-based processing pipeline for high-definition stereo video
    Pierre Greisen
    Simon Heinzle
    Markus Gross
    Andreas P Burg
    EURASIP Journal on Image and Video Processing, 2011
  • [8] An FPGA-based processing pipeline for high-definition stereo video
    Greisen, Pierre
    Heinzle, Simon
    Gross, Markus
    Burg, Andreas P.
    EURASIP JOURNAL ON IMAGE AND VIDEO PROCESSING, 2011,
  • [9] FPGA-based reconfigurable adaptive FEC
    Shimizu, K
    Uchida, J
    Miyaoka, Y
    Togawa, N
    Yanagisawa, M
    Ohtsuki, T
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2004, E87A (12) : 3036 - 3046
  • [10] Reconfigurable PUFs for FPGA-based SoCs
    Gehrer, Stefan
    Sigl, Georg
    2014 14TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC), 2014, : 140 - 143