Field-plate engineering for HFETs

被引：93
作者：
Karmalkar, S [1 ]
Shur, MS
Simin, G
Khan, MA
机构：
[1] Indian Inst Technol, Dept Elect Engn, Madras 600036, Tamil Nadu, India
[2] Rensselaer Polytech Inst, Dept Comp Sci & Elect Engn, Troy, NY 12180 USA
[3] Univ S Carolina, Dept Elect Engn, Columbia, SC 29208 USA
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2005年 / 52卷 / 12期
基金：
美国国家科学基金会;
关键词：
analytical modeling; field plate; heterostructure field effect transistor (HFET);
D O I：
10.1109/TED.2005.859568
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper reports on the analytical approach for designing field plates for reducing the electric field in the channel and at the surface of heterostructure field-effect transistors (HFETs) for a given drain voltage, with the smallest possible increase of the gate capacitance. The analytical calculations for GaN-based HFETs are in good agreement with the two-dimensional numerical simulations.
引用
收藏
页码：2534 / 2540
页数：7
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