WS2 transistors on 300 mm wafers with BEOL compatibility

被引：0

作者：

Schram, T. ^{[1
]}

Smets, Q. ^{[1
]}

Groven, B. ^{[1
]}

Heyne, M. H. ^{[1
]}

Kunnen, E. ^{[1
]}

Thiam, A. ^{[1
]}

Devriendt, K. ^{[1
]}

Delabie, A. ^{[1
]}

Lin, D. ^{[1
]}

Lux, M. ^{[1
]}

Chiappe, D. ^{[1
]}

Asselberghs, I. ^{[1
]}

Brus, S. ^{[1
]}

Huyghebaert, C. ^{[1
]}

Sayan, S. ^{[1
]}

Juncker, A. ^{[2
]}

Caymax, M. ^{[1
]}

Radu, I. P. ^{[1
]}

机构：

[1] IMEC, D,Kapeldreef 75, B-3001 Leuven, Belgium

[2] COVENTOR, 3 Ave Quebec, F-91140 Villebon Sur Yvette, France

来源：

2017 47TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC) | 2017年

关键词：

WS2; TMD; 2D; transistor; BEOL; 300; mm; GRAPHENE; FILMS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

For the first time, WS2-based transistors have been successfully integrated in a 300 mm pilot line using production tools. The 2D material was deposited using either area selective chemical vapor deposition (CVD) or atomic layer deposition (ALD). No material transfer was required. The major integration challenges are the limited adhesion and the fragility of the few-monolayer 2D material. These issues are avoided by using a sacrificial Al2O3 capping layer and by encapsulating the edges of the 2D material during wet processing. The WS2 channel is contacted with Ti/TiN side contacts and an industry-standard back end of line (BEOL) flow. This novel low-temperature flow is promising for integration of back-gated 2D transistors in the BEOL.

引用

页码：212 / 215

页数：4

共 50 条

[31] High-Performance WS2 MOSFETs with Bilayer WS2 Contacts
Jin, Lun
Wen, Jiaxuan
Odlyzko, Michael
Seaton, Nicholas
Li, Ruixue
Haratipour, Nazila
Koester, Steven J.
ACS OMEGA, 2024, 9 (29): : 32159 - 32166
[32] Wafer-scale integration of double gated WS2-transistors in 300mm Si CMOS fab
Asselberghs, I
Smets, Q.
Schram, T.
Groven, B.
Verreck, D.
Afzalian, A.
Arutchelvan, G.
Gaur, A.
Cott, D.
Maurice, T.
Brems, S.
Kennes, K.
Phommahaxay, A.
Dupuy, E.
Radisic, D.
De Marneffe, J-F
Thiam, A.
Li, W.
Devriendt, K.
Huyghebaert, C.
Lin, D.
Caymax, M.
Morin, P.
Radu, I. P.
2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2020,
[33] Preparation and tribological properties of WS2 and WS2/TiO2 nanoparticles
Lu, Ziyan
Cao, Zhenzhen
Hu, Enzhu
Hu, Kunhong
Hu, Xianguo
TRIBOLOGY INTERNATIONAL, 2019, 130 : 308 - 316
[34] 300mm Prime and the prospect for 450mm wafers
Jones, Scotten W.
SOLID STATE TECHNOLOGY, 2009, 52 (12) : 14 - 15
[35] Fabrication of Medium Power Insulated Gate Bipolar Transistors Using 300 mm Magnetic Czochralski Silicon Wafers
Schulze, Hans-Joachim
Oefner, Helmut
Niedernostheide, Franz-Josef
Luekermann, Florian
Schulz, Andreas
PHYSICA STATUS SOLIDI A-APPLICATIONS AND MATERIALS SCIENCE, 2019, 216 (17):
[36] Vertical WS2/SnS2 van der Waals Heterostructure for Tunneling Transistors
Jiaxin Wang
Rundong Jia
Qianqian Huang
Chen Pan
Jiadi Zhu
Huimin Wang
Cheng Chen
Yawen Zhang
Yuchao Yang
Haisheng Song
Feng Miao
Ru Huang
Scientific Reports, 8
[37] Silicon crystals for future requirements of 300 mm wafers
Dornberger, E
Virbulis, J
Hanna, B
Hoelzl, R
Daub, E
von Ammon, W
JOURNAL OF CRYSTAL GROWTH, 2001, 229 (01) : 11 - 16
[38] A low cost bumping process for 300 mm wafers
Oppert, T
Teutsch, T
Zakel, E
Tovar, D
1999 INTERNATIONAL SYMPOSIUM ON MICROELECTRONICS, PROCEEDINGS, 1999, 3906 : 34 - 38
[39] Metrology of 300 mm silicon wafers: Challenges and results
Wagner, P
CHARACTERIZATION AND METROLOGY FOR ULSI TECHNOLOGY, 1998, 449 : 153 - 160
[40] In-line measurement of Xj on 300 mm wafers
Corcoran, S
Gillespie, P
Segovia, M
Borden, P
IIT2002: ION IMPLANTATION TECHNOLOGY, PROCEEDINGS, 2003, : 169 - 172

← 1 2 3 4 5 →