Improvement of Positive Bias Temperature Instability Characteristic in GaN MOSFETs by Control of Impurity Density in SiO2 Gate Dielectric

被引：0

作者：

Yonehara, T. ^{[1
]}

Kajiwara, Y. ^{[1
]}

Kato, D. ^{[1
]}

Uesugi, K. ^{[1
]}

Shimizu, T. ^{[1
]}

Nishida, Y. ^{[1
]}

Ono, H. ^{[1
]}

Shindome, A. ^{[1
]}

Mukai, A. ^{[1
]}

Yoshioka, A. ^{[2
]}

Kuraguchi, M. ^{[1
]}

机构：

[1] Toshiba Co Ltd, Corp Res & Dev Ctr, Kawasaki, Kanagawa, Japan

[2] Toshiba Device & Semicond Corp, Adv Discrete Dev Ctr, Kawasaki, Kanagawa, Japan

来源：

2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2017年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Threshold voltage shift of GaN MOSFET in positive bias temperature instability test was drastically suppressed by reducing certain impurity densities in SiO2 gate dielectric. An analysis to estimate the charge trap level showed electron traps in the gate dielectric caused the threshold voltage shift in GaN MOSFETs. Moreover, impurities, which formed the electron traps in SiO2, were controlled by heat treatment after SiO2 deposition, and the threshold voltage shift characteristic was improved by the reduction of the impurity densities.

引用

页数：4

共 50 条

[21] RAPID THERMAL ANNEALED CHEMICAL VAPOR-DEPOSITED SIO2 AS GATE DIELECTRIC IN SILICON MOSFETS
ANG, S
WILSON, S
JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1986, 133 (03) : C106 - C106
[22] Negative Bias Temperature Instability (NBTI) in SiO2 and SiON gate dielectrics understood through disorder-controlled kinetics
Kaczer, B
Arkhipov, V
Jurczak, M
Groeseneken, G
MICROELECTRONIC ENGINEERING, 2005, 80 : 122 - 125
[23] Comparison of positive and negative bias-temperature instability on MOSFETs with HfO2/LaOx and HfO2/AlOx dielectric stacks
Lu, Chun-Chang
Chang-Liao, Kuei-Shu
Tsao, Che-Hao
Wang, Tien-Ko
SOLID-STATE ELECTRONICS, 2010, 54 (11) : 1474 - 1478
[24] Positive Bias Instability in ZnO TFTs with Al2O3 Gate Dielectric
Bolshakov, Pavel
Rodriguez-Davila, Rodolfo A.
Quevedo-Lopez, Manuel
Young, Chadwin D.
2019 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2019,
[25] Positive-Bias Temperature Instability Improvement of Poly-Si Thin-Film Transistor With HfO2 Gate Dielectric by Ammonia Plasma Treatment
Ma, William Cheng-Yu
Lin, Zheng-Yi
Huang, Yao-Sheng
Huang, Bo-Siang
Wu, Zheng-Da
IEEE TRANSACTIONS ON PLASMA SCIENCE, 2016, 44 (12) : 3153 - 3157
[26] Net negative charge in low-temperature SiO2 gate dielectric layers
Boogaard, A.
Kovalgin, A. Y.
Wolters, R. A. M.
MICROELECTRONIC ENGINEERING, 2009, 86 (7-9) : 1707 - 1710
[27] Lateral profiling of gate dielectric damage by off-state stress and positive-bias temperature instability
Lee, Geon-Beom
Kim, Choong-Ki
Bang, Tewook
Yoo, Min-Soo
Choi, Yang-Kyu
MICROELECTRONICS RELIABILITY, 2021, 127
[28] Effects of PECVD SiO2 Gate Dielectric Thickness on Recessed AlGaN/GaN MOS-HFETs
Kim, Hyun-Seop
Jang, Won-Ho
Eom, Su-Keun
Han, Sang-Woo
Kim, Hyungtak
Seo, Kwang-Seok
Cho, Chun-Hyung
Cha, Ho-Young
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2018, 18 (02) : 187 - 192
[29] Negative-Bias Temperature Instability in Gate-All-Around Silicon Nanowire MOSFETs: Characteristic Modeling and the Impact on Circuit Aging
Liu, Changze
Yu, Tao
Wang, Runsheng
Zhang, Liangliang
Huang, Ru
Kim, Dong-Won
Park, Donggun
Wang, Yangyuan
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57 (12) : 3442 - 3450
[30] Advanced MOSFETs using HfTaON/SiO2 gate dielectric and TaN metal gate with excellent performances for low standby power application
Yu, XF
Zhu, CX
Yu, MB
Li, MF
Chin, A
Tung, CH
Gui, D
Kwong, DL
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST, 2005, : 31 - 34

← 1 2 3 4 5 →