Wafer level hermetic sealing of MEMS devices with vertical feedthroughs using anodic bonding

被引:52
作者
Torunbalci, Mustafa Mert [1 ]
Alper, Said Emre [1 ]
Akin, Tayfun [2 ,3 ]
机构
[1] Middle E Tech Univ, MEMS Res & Applicat Ctr, TR-06530 Ankara, Turkey
[2] Middle E Tech Univ, MEMS Res & Applicat Ctr, Dept Elect & Elect Engn, TR-06531 Ankara, Turkey
[3] Micro & Nano Technol Grad Program, TR-06531 Ankara, Turkey
关键词
Wafer level hermetic packaging; Vertical feedthroughs; Anodic bonding; Advanced MEMS (aMEMS) process;
D O I
10.1016/j.sna.2015.01.034
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a new method for wafer-level hermetic packaging of MEMS devices using a relatively low temperature anodic bonding technique applied to the recently developed advanced MEMS (aMEMS) process. The aMEMS process uses vertical feedthroughs formed on an SOI cap wafer, eliminating the need for any complex via-refill or trench-refill steps while forming the vertical feedthroughs. The hermetic sealing process is achieved at 350 degrees C by using an anodic bonding potential of 600 V. The bonding process does not require any sealing material on neither the cap nor the sensor wafer. The packaging yield is experimentally verified to be 94% for 4 wafers packaged up to date, and the cavity pressure is measured to be as low as 1 mTorr with successfully activated Titanium thin film getter. The cavity pressure can be set to different levels ranging from 1 mTorr up to 5 Torr, simply by varying the outgassing period and utilization of the getter material, enabling the proposed method be used for various types of MEMS devices with different pressure requirements. The pressure inside the encapsulated cavities has been monitored for 6 months since the first prototypes, and it is observed that pressure is stable below 5 mTorr throughout this period. The shear strength of 6 packages is measured to be above 10 MPa, whereas the shear failure occurs not at the bonding interface but the vertical feedthroughs, which have lower strength compared to the bonding region. The robustness of the packages is tested by subjecting them to cyclic thermal tests between 100 degrees C and 25 degrees C, and no degradation is observed in the hermeticity of the packages at the end of this period. The vacuum level of the packages is also verified to be unchanged by storing the packages at 150 degrees C for 24 h. Moreover, it is experimentally verified that the hermeticity of the packaged chips can withstand ultra-high temperature shocks as high as 400 degrees C for 5 min. (C) 2015 Elsevier B.V. All rights reserved.
引用
收藏
页码:169 / 176
页数:8
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