A 5.8GHz 9.5 dBm Class-E Power Amplifier for DSRC Applications

被引：0

作者：

Qaragoez, Yasser Mohammadi ^{[1
]}

Ali, Imran ^{[1
]}

Kim, Seong Jin ^{[1
]}

Lee, Kang-Yoon ^{[1
]}

机构：

[1] Sungkyunkwan Univ, Dept Elect & Comp Engn, Suwon, South Korea

来源：

2019 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | 2019年

基金：

新加坡国家研究基金会;

关键词：

electronic toll collection system (ETCS); Class-E; analog delay cell; CMOS power amplifier; dedicated short range communication (DSRC);

D O I：

10.1109/isocc47750.2019.9027646

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a 5.8 GHz Class-E power amplifier with analog delay cell to improve the spurious is presented for dedicated short-range communication (DSRC) transceivers. The power amplifier consists of 2-stage Class-AB as driver stages and a cascode Class-E topology for the PA core. To improve the spurious of the PA an analog delay cell with 128 core cells is implemented which has achieved same fall time and rise time, less area and simplicity in comparison to digital delay cells. Realized in a 0.13-mu m CMOS technology, the power amplifier achieves 9.5 dBm and 57 dBc output power and adjacent channel power ratio, respectively. The Occupied bandwidth (OCB) is 64kHz while dissipating 76 mA with 3.3V supply voltage.

引用

页码：202 / 203

页数：2