Low back-reflection CMOS-compatible grating coupler for perfectly vertical coupling

In view of high volume manufacturing of silicon based photonic-integrated-circuits (Si-PICs), CMOS compatible low-cost fabrication processes as well as simplified packaging methods are imperatively needed. Silicon-on-Insulator (SOI) based grating couplers (GCs) have attracted attention as the key components for providing optical interfaces to Si-PICs due their fabrication simplicity compared to the edge coupling alternatives. GCs based on perfectly vertical coupling scheme become essential by introducing substantial savings in the packaging cost as no angular configurations are required but at the expense of high coupling efficiency values due to the second order diffraction. In this context, research efforts concentrated on designing GCs with minimized back reflection into the waveguide yet employing more than one etching steps or rather complex fabrication processes. Herein, we propose a fully etched CMOS compatible non-uniform one-dimensional (1D) GC for perfectly vertical coupling with low back reflected optical power by means of numerical simulations. A particle-swarm-optimization (PSO) algorithm was deployed in conjunction with a commercially available 2D finite-difference-time-domain (FDTD) method to maximize the coupling efficiency to a SMF fiber for TM polarization. The design parameters were restricted to the period length and the filling factor while the minimum feature size was 80 nm. A peak coupling loss of 4.4 dB at 1553 nm was achieved with a 1-dB bandwidth of 47 nm and a back reflection of -20 dB. The coupling tolerance to fabrication errors was also investigated.