A 4.5 fJ/conversion-step 10-bit 0.6V Asynchronous SAR ADC for Battery-free Miniature Sensor Nodes in 65nm CMOS

被引:0
|
作者
Dadashi, Ali [1 ]
Berg, Yngvar [1 ]
Mirmotahari, Omid [1 ]
机构
[1] Univ Oslo, Dept Informat, Oslo, Norway
来源
PROCEEDINGS OF THE 2019 26TH INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (MIXDES 2019) | 2019年
关键词
Ultra-Low-power (ULP); successive-approximation-register (SAR) analog-to-digital converter (ADC);
D O I
10.23919/mixdes.2019.8787150
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a 0.6-V energy-efficient 10-bit Asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with internal clock generator. Also a multiplexer is designed to serially transfer the output bits to outside the chip. A novel capacitive array also is proposed in this paper. The prototype is designed and fabricated in a 65-nm CMOS with a core size of 290 mu m x 130 mu m (0.0377 mm2). At 2.4 KS/s and Nyquist rate input, it consumes 4 nW at 0.6-V supply with an achieved signal-to-noise-and distortion ratio of 53.2 dB and a resulting figure of merit (FOM) of 4.5 fJ/conv.-step. Prototyped in a low-power 65 nm CMOS process, the ADC achieves an INL and DNL of 1.57 LSB and 0.95 LSB respectively at 0.6 V supply.
引用
收藏
页码:129 / 132
页数:4
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