A practical transistor-level dual threshold voltage assignment methodology

Leakage power has become one of the most critical design concerns for the system-level chip designer Multi-threshold techniques have been used to reduce runtime leakage power without sacrificing performance. In this paper we present an effective and scalable transistor-level V-th assignment approach and show leakage reduction over standard cell-level V-th assignment. The main disadvantage of transistor-level Vth assignment is increased cell library size and characterization effort. lit comparison to previous approaches, our approach yields better solution quality, requires smaller cell library, is more accurate in considering the impact Of V-th assignment on propagation delay, slew (transition delay) and capacitance, and is significantly faster.