A comprehensive three-phase step voltage regulator model with efficient implementation in the Z-bus power flow

This paper presents a comprehensive three-bus equivalent circuit model of three-phase step voltage regulators. The proposed model can be efficiently integrated in the Z-bus power flow method and can accurately simulate any configuration of step voltage regulators. In contrast to the conventional step voltage regulator models that include the tap variables inside the YBUS matrix of the network, the proposed model simulates them in the form of current sources, outside the YBUS matrix. As a result, the re-factorization of the YBUS matrix is avoided after every tap change reducing significantly the computational burden of the power flow. Furthermore, possible convergence issues caused by the low impedance of step voltage regulators are addressed by introducing fictitious impedances, without, however, affecting the accuracy of the model. The results of the proposed step voltage regulator model are compared against well-known commercial softwares such as Simulink and OpenDSS using the IEEE 4-Bus and an 8-Bus network. According to the simulations, the proposed model outputs almost identical results with Simulink and OpenDSS confirming its high accuracy. Furthermore, the proposed 3-bus equivalent model is compared against a recently published conventional step voltage regulator model in the IEEE 8500Node test feeder. Simulation results indicate that the proposed step voltage regulator model produces as accurate results as the conventional one, while its computation time is significantly lower. More specifically, in the large IEEE 8500-node network consisting of four SVRs, the proposed model can reduce the computation time of power flow around one minute for every tap variation. Therefore, the proposed step voltage regulator model can constitute an efficient simulation tool in applications where subsequent tap variations are required.