共 11 条
[1]
Fukuda K., 2011, 2011 IEEE International Solid-State Circuits Conference (ISSCC 2011), P198, DOI 10.1109/ISSCC.2011.5746280
[2]
Jae-Duk Lee, 2006, 21st Non-Volatile Semiconductor Memory Workshop. (IEEE Cat. No. 06EX1246), P31, DOI 10.1109/.2006.1629481
[4]
Kamigaichi T, 2008, INT EL DEVICES MEET, P827
[5]
Ki-Tae Park, 2011, 2011 IEEE International Solid-State Circuits Conference (ISSCC 2011), P212, DOI 10.1109/ISSCC.2011.5746287
[6]
LEE CH, 2010, IEDM, P98
[7]
Prall K., 2010, IEDM, P102
[8]
A novel isolation-scaling technology for NAND EEPROMs with the minimized program disturbance
[J].
INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST,
1997,
:291-294
[9]
SHIROTA R, 2000, P NONV SEM MEM WORKS, P22
[10]
Tae-yun Kim, 2011, 2011 IEEE International Solid-State Circuits Conference (ISSCC 2011), P202, DOI 10.1109/ISSCC.2011.5746282