Toward Real-Time Ray Tracing: A Survey on Hardware Acceleration and Microarchitecture Techniques

被引:35
作者
Deng, Yangdong [1 ]
Ni, Yufei [2 ]
Li, Zonghui [1 ]
Mu, Shuai [2 ,3 ]
Zhang, Wenjun [2 ]
机构
[1] Tsinghua Univ, Sch Software Engn, Beijing, Peoples R China
[2] Tsinghua Univ, Inst Microelect, Beijing, Peoples R China
[3] Qualcomm, San Diego, CA USA
基金
美国国家科学基金会;
关键词
Design; Algorithms; Performance; Ray tracing; GPU; spatial data structure; construction; traversal; KD-TREE CONSTRUCTION; ARCHITECTURE;
D O I
10.1145/3104067
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Ray tracing has long been considered as the next-generation technology for graphics rendering. Recently, there has been strong momentum to adopt ray tracing-based rendering techniques on consumer-level platforms due to the inability of further enhancing user experience by increasing display resolution. On the other hand, the computing workload of ray tracing is still overwhelming. A 10-fold performance gap has to be narrowed for real-time applications, even on the latest graphics processing units (GPUs). As a result, hardware acceleration techniques are critical to delivering a satisfying level performance while at the same time meeting an acceptable power budget. A large body of research on ray-tracing hardware has been proposed over the past decade. This article is aimed at providing a timely survey on hardware techniques to accelerate the ray-tracing algorithm. First, a quantitative profiling on the ray-tracing workload is presented. We then review hardware techniques for the main functional blocks in a ray-tracing pipeline. On such a basis, the ray-tracing microarchitectures for both ASIC and processors are surveyed by following a systematic taxonomy.
引用
收藏
页数:41
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