共 50 条
- [31] Design of fixed-point hardware accelerator word length in SoC based on statistical analysis Guti Dianzixue Yanjiu Yu Jinzhan/Research and Progress of Solid State Electronics, 2007, 27 (02): : 240 - 245
- [32] A 35 μW 1.1V gate array 8x8 IDCT processor for video-telephony PROCEEDINGS OF THE 1998 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING, VOLS 1-6, 1998, : 2993 - 2996
- [33] A new 2-D 8x8 DCT/IDCT core design using group distributed arithmetic PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II: COMMUNICATIONS-MULTIMEDIA SYSTEMS & APPLICATIONS, 2003, : 752 - 755
- [34] A parameterized power-aware IP core generator for the 2-D 8x8 DCT/IDCT 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, 2004, : 769 - 772
- [36] H.264 8x8 Inverse Transform Architecture Optimization GLSVLSI'14: PROCEEDINGS OF THE 2014 GREAT LAKES SYMPOSIUM ON VLSI, 2014, : 83 - 84
- [37] A FIXED-POINT FAST FOURIER TRANSFORM ERROR ANALYSIS IEEE TRANSACTIONS ON AUDIO AND ELECTROACOUSTICS, 1969, AU17 (02): : 151 - &
- [38] FIXED-POINT ERROR ANALYSIS FOR THE FAST COSINE TRANSFORM CA-DSP 89, VOLS 1 AND 2: 1989 INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SIGNAL PROCESSING, 1989, : 375 - 378
- [39] FIXED-POINT ERROR ANALYSIS OF THE NORMALIZED LADDER ALGORITHM IEEE TRANSACTIONS ON ACOUSTICS SPEECH AND SIGNAL PROCESSING, 1983, 31 (05): : 1177 - 1191