Fixed-point error analysis and word length optimization of 8x8 IDCT architectures

被引:0
|
作者
Kim, S [1 ]
Sung, W
机构
[1] LG Corp Inst Technol, Informat Technol Lab, Seoul, South Korea
[2] Seoul Natl Univ, Sch Elect Engn, Seoul 151742, South Korea
关键词
distributed arithmetic; fixed-point error analysis; IDCT; IEEE Standard 1180-1990; word length optimization;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Complete fixed-point error models that include the coefficient quantization are derived for two popular 8 x 8 two-dimensional (2-D) IDCT architectures; one is based on distributed arithmetic. and the other is the multiplier-adder chain. The error models are evaluated in the integer domain to accurately measure the effects of rounding. The analysis results show that the overall mean-square error performance (OMSE) is the most critical condition for meeting the IEEE specification (IEEE Std. 1180-1990) when the rounding scheme is employed, On the other hand, the mean error effects (OME and PME) are dominant for truncation. Finally, the analysis results are compared with those of bit-accurate simulation.
引用
收藏
页码:935 / 940
页数:6
相关论文
共 50 条
  • [31] Design of fixed-point hardware accelerator word length in SoC based on statistical analysis
    Zhou, Fan
    Shi, Longxing
    Yang, Jun
    Guti Dianzixue Yanjiu Yu Jinzhan/Research and Progress of Solid State Electronics, 2007, 27 (02): : 240 - 245
  • [32] A 35 μW 1.1V gate array 8x8 IDCT processor for video-telephony
    Rambaldi, R
    Uguzzoni, A
    Guerrieri, R
    PROCEEDINGS OF THE 1998 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING, VOLS 1-6, 1998, : 2993 - 2996
  • [33] A new 2-D 8x8 DCT/IDCT core design using group distributed arithmetic
    Guo, JI
    Chen, JW
    Chen, HC
    PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II: COMMUNICATIONS-MULTIMEDIA SYSTEMS & APPLICATIONS, 2003, : 752 - 755
  • [34] A parameterized power-aware IP core generator for the 2-D 8x8 DCT/IDCT
    Ju, RC
    Chen, JW
    Guo, JI
    Chen, TF
    2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, 2004, : 769 - 772
  • [35] A cost-effective architecture for 8x8 two-dimensional DCT/IDCT using direct method
    Lee, YP
    Chen, TH
    Chen, LG
    Chen, MJ
    Ku, CW
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 1997, 7 (03) : 459 - 467
  • [36] H.264 8x8 Inverse Transform Architecture Optimization
    Pereira, Fabio
    Borin, Andre
    Susin, Altamiro
    GLSVLSI'14: PROCEEDINGS OF THE 2014 GREAT LAKES SYMPOSIUM ON VLSI, 2014, : 83 - 84
  • [37] A FIXED-POINT FAST FOURIER TRANSFORM ERROR ANALYSIS
    WELCH, PD
    IEEE TRANSACTIONS ON AUDIO AND ELECTROACOUSTICS, 1969, AU17 (02): : 151 - &
  • [38] FIXED-POINT ERROR ANALYSIS FOR THE FAST COSINE TRANSFORM
    HE, YJ
    WANG, ZD
    CA-DSP 89, VOLS 1 AND 2: 1989 INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SIGNAL PROCESSING, 1989, : 375 - 378
  • [39] FIXED-POINT ERROR ANALYSIS OF THE NORMALIZED LADDER ALGORITHM
    SAMSON, CG
    REDDY, VU
    IEEE TRANSACTIONS ON ACOUSTICS SPEECH AND SIGNAL PROCESSING, 1983, 31 (05): : 1177 - 1191
  • [40] NOVEL VLSI IMPLEMENTATION OF (8X8) POINT 2-D DCT
    MCGOVERN, FA
    WOODS, RF
    YAN, M
    ELECTRONICS LETTERS, 1994, 30 (08) : 624 - 626