Compact modeling of suspended gate FET

被引：6

作者：

Chauhan, Y. S. ^{[1
]}

Tsamados, D. ^{[1
]}

Abele, N. ^{[1
,2
]}

Eggimann, C. ^{[3
]}

Declercq, M. ^{[1
]}

Ionescu, A. M. ^{[1
]}

机构：

[1] Ecole Polytech Fed Lausanne, CH-1015 Lausanne, Switzerland

[2] ST Microelect, Crolles, France

[3] Stanford Univ, Ctr Integrated Syst, Stanford, CA 94305 USA

来源：

21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS | 2008年

关键词：

D O I：

10.1109/VLSI.2008.11

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

For the first time, a compact model for Suspended Gate (SG) FET valid for entire bias range is proposed. The model is capable of simulating both pull-in and pull-out effects, which are the two important phenomena of this device. A novel hybrid numerical simulation approach combining ANSYS Multiphysics and ISE-DESSIS in a self-consistent system is developed. The model is then validated on this numerical device simulation of SGFET. The model shows excellent performance over the entire drain and gate voltage range. The model has been implemented in Verilog-A code and tested on ELDO and Spectre simulators, which makes it useful for circuit simulations using SGFET devices.

引用

页码：119 / +

页数：2

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