A 180-nm 1.2-V LO Divider with Quadrature Phase Generation for Low-Power 868-915 MHz SRD-Band Applications

This paper proposes an LO-divider circuit with non-overlapping quadrature phase generation in 180 nm triple-well CMOS. It addresses the problem of dealing with a reduced supply voltage for power reduction, but still maintaining a sufficient maximum operating frequency for radio-frequency applications. The clock division and phase generation is done by using cross-connected D-latches. A brief overview of different latch architectures is given and compared concerning their power consumption and maximum frequency. Simulation results of an RC-extracted layout are presented, which show a current consumption of 400 mu A at 868 MHz output frequency.