Ribbon bonding - A scalable interconnect for power QFN packages

Continuous improvements in Silicon technology enable an ongoing reduction in Silicon-intrinsic on-state resistance, especially for low voltage MOSFETs, or shrinking the die size for a given on-state resistance. At the same time, new features and functionality create a need for power packages that more efficiently use the available space in many end applications. Smaller packages and multi-chip packages save system space and require less packaging material, both of which are main cost factors. The Power Quad Flat-Pack No-Lead (PQFN) package design appears to be the most promising standard package design to support these needs for improved performance, smaller size, and lower cost. But none of the interconnect techniques established in the existing power package families, like TO-XXX and power SO-XX, large Aluminum (Al) wire bonding, fine wire Gold (Au) and Copper (Cu) ball bonding, or Cu clip/strap bonding, will allow covering the complete spectrum of PQFN package sizes effectively. This paper describes the ribbon interconnect design and its characteristics. It demonstrates its effectiveness over the complete range of PQFN package sizes from 2x2mm. to 12x12mm, for present and future Silicon performance levels. Interconnect resistance calculations are used to compare different configurations and deduce design recommendations. The results of the study point to ribbon bonding as the most effective standard power interconnect technique, especially considering the trend towards decreasing die and package sizes, and indicate a good fit with the PQFN package concept.