Band-engineered low PMOS VT with high-K/metal gates featured in a dual channel CMOS integration scheme

被引：52

作者：

Harris, H. Rusty ^{[2
]}

Kalra, Pankaj ^{[5
]}

Majhi, Prashant ^{[3
]}

Hussain, Muhammed ^{[1
]}

Kelly, David ^{[1
]}

Oh, Jungwoo ^{[1
]}

He, Dawei ^{[1
]}

Smith, Casey ^{[1
]}

Barnett, Joel ^{[1
]}

Kirsch, Paul D. ^{[4
]}

Gebara, Gabriel ^{[6
]}

Jur, Jess ^{[7
]}

Lichtenwalner, Daniel ^{[7
]}

Lubow, Abigail ^{[8
]}

Ma, T. P. ^{[8
]}

Sung, Guangyu

Thompson, Scott ^{[9
]}

Lee, Byoung Hun ^{[4
]}

Tseng, Hsing Huang ^{[1
]}

Jammy, Raj ^{[4
]}

机构：

[1] SEMATECH, Austin, TX USA

[2] AMD, Sunnyvale, CA 94088 USA

[3] Intel, Santa Clara, CA USA

[4] IBM Corp, Armonk, NY USA

[5] Univ Calif Berkeley, Berkeley, CA 94720 USA

[6] ATDF, New York, NY USA

[7] NC State Univ, Raleigh, NC USA

[8] Yale Univ, New Haven, CT USA

[9] Univ Florida, Gainesville, FL USA

来源：

2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2007年

关键词：

D O I：

10.1109/VLSIT.2007.4339763

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Using strained SiGe on Si, the threshold voltage of high K PMOS devices is reduced by as much as 300mV. The 80nm devices exhibit excellent short channel characteristics such as DIBL and GIDL. For the first time a dual channel scheme using standard activation anneal temperature is applied that allows La2O3 capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high K and metal gates for 32nm node and beyond.

引用

页码：154 / +

页数：2

共 10 条

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