Elastic buffer evaluation for link pipelining under process variation

被引:5
作者
Adl, Seyed Mohamad Taghi [1 ]
Mitzaei, Mohammad [1 ]
Mohammadi, Siamak [1 ,2 ]
机构
[1] Univ Tehran, Sch ECE, Dependable Syst Design Lab, Tehran, Iran
[2] Inst Fundamental Sci IPM, Sch Comp Sci, Tehran, Iran
关键词
CHANNEL BUFFERS; ON-CHIP; NETWORKS; POWER; PERFORMANCE; EFFICIENCY; FLOW;
D O I
10.1049/iet-cds.2017.0394
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Network-on-chip (NoC) adopted for many-core intercommunications may face long link delay and power consumption limitations. A proven solution is to segment long links with storage elements or repeaters. Besides, a new design paradigm called elastic has been considered in the literature, which seems suitable for NoC designs. In this study, the authors explore the benefit of various elastic-buffer (EB) structures to be used for link pipelining. They study elastic handshaking protocols and explore various elastic buffer designed to be used in NoC era. They propose to use synchronous elastic flow (SELF) handshaking protocol for link pipelining. Results show elastic buffer structure based on SELF-handshaking protocol, which can run at least with 21% higher frequency, has 25% less delay and consumes 8% less power compared with other proposed designs. They have explored the process variation issues with various scenarios on seven different structures. They have improved the SELF-elastic buffer, which is more resilient against process variation, proposing two new structures. The new proposed structures exhibit about 5% better performance and 13% less power delay product variation in average.
引用
收藏
页码:645 / 654
页数:10
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