Expressing embedded systems configurations at high abstraction levels with UML MARTE profile: Advantages, limitations and alternatives

被引:23
作者
Quadri, Imran Rafiq [1 ]
Gamatie, Abdoulaye [1 ]
Boulet, Pierre [1 ]
Meftali, Samy [1 ]
Dekeyser, Jean-Luc [1 ]
机构
[1] INRIA Lille Nord Europe, LIFL, USTL, CNRS, Lille, France
关键词
Embedded systems; Systems-on-Chips (SoCs); High abstraction levels; MDE; UML; MARIE; Configurations; QoS;
D O I
10.1016/j.sysarc.2012.01.001
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Embedded systems have become an essential aspect of our professional and personal lives. From avionics, transport and telecommunication systems to general commercial appliances such as smart phones, high definition TVs and gaming consoles; it is difficult to find a domain where these systems have not made their mark. Moreover, Systems-on-Chips (SoCs) which are considered as an integral solution for designing embedded systems, offer advantages such as run-time reconfiguration that can change system configurations during execution, depending upon Quality-of-Service (QoS) criteria such as performance and energy levels. This article deals with aspects related to modeling of these configurations, useful for describing various states of an embedded system, from both structural and operational viewpoints. Our proposal adapts a high abstraction level approach based on the principles of Model-Driven Engineering (MDE) and takes into account the UML MARTE profile for modeling of real-time and embedded systems. Elevating the design abstraction levels help to increase design productivity and achieve execution platform independence, among other advantages. The article details the current proposition of configurations in MARIE via some examples, and points out the advantages as well as some limitations, mainly concerning the semantic aspects of the defined concepts. Finally, we report our experiences on the modeling of an alternate notion of configurations and execution modes within the MARTE compliant Gaspard2 SoC Co-Design framework that has been successful for the design as well as implementation of FPGA based SoCs. (C) 2012 Elsevier B.V. All rights reserved.
引用
收藏
页码:178 / 194
页数:17
相关论文
共 42 条
  • [1] AADL, 2006, AADL ARCHITECTURE AN
  • [2] Andre C., 2003, SYNCHRONOUS LANGUAGE
  • [3] [Anonymous], 2009, MDA COD GEN
  • [4] [Anonymous], UML PROF SYST CHIP S
  • [5] Arpinen T., 2010, 1 WORKSH MOD BAS ENG
  • [6] Ben Atitallah R., 2008, THESIS USTL LILLE
  • [7] Colaco J.-L., 2006, ACM INT C EMB SOFTW
  • [8] High-level synthesis under I/O timing and memory constraints
    Coussy, P
    Corre, G
    Bomel, P
    Senn, E
    Martin, E
    [J]. 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 680 - 683
  • [9] DaRT team, 2010, GASPARD SOC FRAM
  • [10] MARTE:: Also an UML profile for modeling AADL applications
    Faugere, Madeleine
    Bourbeau, Thimothee
    De Simone, Robert
    Gerard, Sebastien
    [J]. 12TH IEEE INTERNATIONAL CONFERENCE ON ENGINEERING COMPLEX COMPUTER SYSTEMS, PROCEEDINGS, 2007, : 359 - 364