Design and demonstration of a 4 x 4 SFQ network switch prototype system and 10-Gbps bit-error-rate measurement

We developed a 4 x 4 SFQ network switch prototype system and demonstrated its operation at 10 Gbps. The system's core is composed of two SFQ chips: a 4 x 4 switch and a 6-channel voltage driver. The 4 x 4 switch chip contained both a switch fabric (i.e. a data path) and a switch scheduler (i.e. a controller). Both chips were attached to a multichip-module (MCM) carrier, which was then installed in a cryocooled system with 32 10-Gbps ports. Each chip contained about 2100 Josephson junctions on a 5-mm x 5-mm die. An NEC standard 2.5-kA/cm(2) fabrication process was used for the switch chip. We increased the critical current density to 10/cm(2) for the driver chip to improve speed while maintaining wide bias margins. MCM implementation enabled us to use a hybrid critical current density technology. Voltage pulses were transferred between two chips through passive transmission lines on the MCM carrier. The cryocooled system was cooled down to about 4 K using a two-stage 1-W cryocooler. We correctly operated the whole system at 10 Gbps. The switch scheduler, which is driven by an on-chip clock generator, operated at 40 GHz. The speed gap between SFQ and room temperature devices was filled by on-chip SFQ FIFO buffers or shift registers. We measured the bit error rate at 10 Gbps and found that it was on the order of 10(-13) for the 4 x 4 SFQ switch fabric. In addition, using semiconductor interface circuitry, we built a four-port SFQ Ethernet switch. All the components except for a compressor were installed in a standard 19-inch rack, filling a space 21 U (933.5 mm or 36.75 inches) in height. After four personal computers (PCs) were connected to the switch, we have successfully transferred video data between them.