Analytical Placement with 3D Poisson's Equation and ADMM Based Optimization for Large-Scale 2.5D Heterogeneous FPGAs

被引:0
|
作者
Chen, Jianli [1 ,2 ]
Zhu, Wenxing [2 ]
Yu, Jun [1 ]
He, Lei [3 ]
Chang, Yao-Wen [4 ,5 ]
机构
[1] Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China
[2] Fuzhou Univ, Ctr Discrete Math & Theoret Comp Sci, Fuzhou, Peoples R China
[3] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90024 USA
[4] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan
[5] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan
来源
2019 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) | 2019年
基金
中国国家自然科学基金;
关键词
CONVERGENCE; EFFICIENT; ALGORITHM; DESIGNS;
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
As the design complexity keep increasing, the 2.5D FPGA with large logic capacity has become popular in modern circuit applications. A 2.5D FPGA consists of multiple dies connected through super long lines (SLLs) on an interposer, where each die contains heterogeneous logic blocks and ASIC-like clocking architectures to achieve better skew and timing. To address the crucial SLL issue and the special clocking architecture, this paper presents the first analytical placement algorithm for the 2.5D FPGA with the objective of minimizing the numbers of inter-die SLL signals and intra-die clocking violations simultaneously. Using a lifting dimension technique, we first formulate the 2.5D global placement problem as a three-dimensional continuous and differential minimization problem, where the SLL-aware block distribution is modeled by 3D Poisson's equation and directly solved to obtain an analytical solution. Then, we further reformulate the minimization problem as a separable optimization problem with linear constraints. Based on the proximal alternating direction method of multipliers (ADMM) optimization method, we efficiently optimize the separable subproblems one by one in an alternating fashion. Finally, clock-aware legalization and detailed placement are applied to legalize and further improve our placement results. Compared with the state-of-the-art work, experimental results show that our algorithm can resolve all clocking constraints and reduce the number of SLL crossing signals by 36.9% with similar wirelength in comparable running time.
引用
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页数:8
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