Two-dimensional modeling of the underlap graded-channel FinFET

被引：11

作者：

Chattopadhyay, Ankush ^{[1
]}

Kundu, Atanu ^{[2
]}

Sarkar, Chandan K. ^{[3
]}

Bose, Chayanika ^{[3
]}

机构：

[1] St Thomas Coll Engn & Technol, ECE Dept, Kolkata, India

[2] Heritage Inst Technol, Kolkata, India

[3] Jadavpur Univ, ETCE Dept, Kolkata, India

来源：

JOURNAL OF COMPUTATIONAL ELECTRONICS | 2020年 / 19卷 / 02期

关键词：

FinFET; Surface potential; Threshold voltage; Graded channel; Subthreshold current; GATE; SOI; OPTIMIZATION; PERFORMANCE; DIELECTRICS; RESISTANCE; MOBILITY; MOSFETS;

D O I：

10.1007/s10825-020-01458-w

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The graded n-channel underlap fin-shaped field-effect transistor (FinFET) provides ample scope for future investigation. This device and the effects of the underlap, gate length, and doping concentration of the short channel are analyzed herein using two-dimensional (2-D) modeling. The proposed structure includes four regions, in each of which a potential function is developed by applying boundary conditions on Poisson's equation. The parabolic potential profiles in the graded channel region and the underlap regions are found to depend on the bias at the gate/drain terminals, the doping profile, the channel length, and the underlap length, ensuring the reliability of the device for low-power circuit applications. The results of this analysis are validated against numerical solutions obtained using a 2-D device simulator, revealing an exact match.

引用

页码：688 / 699

页数：12

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