A 10-Gb/s CMOS serial-link receiver using eye-opening monitoring for adaptive equalization and for clock and data recovery

A 10-Gb/s receiver for chip-to-chip communication is presented which employs an eye-opening monitor for both adaptive equalization as well as digital clock and data recovery (CDR). The prototype circuit fabricated in 0.13-mu m CMOS technology consumes about 164 mW (adaptive equalizer and CDR, excluding output buffers) at 1.2 V supply voltage and occupies about 0.39x0.39 mm(2). The CDR fulfills the SONET/SDH jitter tolerance requirements at a 2(31)-1 PRBS and a BER of < 10(-12). Successful adaptive equalization of a 30 cm (12") and 76 cm (30") channel on standard FR4 substrate is also demonstrated.