A 5.5mW 6b 5GS/s 4x-Interleaved 3b/cycle SAR ADC in 65nm CMOS

被引:0
|
作者
Chan, Chi-Hang [1 ]
Zhu, Yan [1 ]
Sin, Sai-Weng [1 ]
Seng-Pan, U. [1 ,2 ]
Martins, R. P. [1 ,3 ]
机构
[1] Univ Macau, Macau, Peoples R China
[2] Synopsys, Macau, Peoples R China
[3] Univ Lisbon, Inst Super Tecn, P-1699 Lisbon, Portugal
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:466 / +
页数:3
相关论文
共 50 条
  • [31] A 0.076mm2 12b 26.5mW 600MS/s 4x-Interleaved Subranging SAR-ΔΣ ADC with On-Chip Buffer in 28nm CMOS
    Venca, Alessandro
    Ghittori, Nicola
    Bosi, Alessandro
    Nani, Claudio
    2016 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2016, 59 : 470 - U662
  • [32] A 5-bit 1.25GS/s 4.7mW Delay-Based Pipelined ADC in 65nm CMOS
    Mesgarani, A.
    Fu, H. P.
    Yan, M.
    Tekin, A.
    Yu, H.
    Ay, S. U.
    2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2013, : 2018 - 2021
  • [33] A 3.65 mW 5 bit 2GS/s Flash ADC with Built-In Reference Voltage in 65nm CMOS Process
    Yang, Jiale
    Chen, Yong
    Qian, He
    Wang, Yan
    Yue, Ruifeng
    2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT-2012), 2012, : 1425 - 1427
  • [34] A 3mW 6b 4GS/s Subranging ADC with Adaptive Offset Adjustable-Comparators
    Yang, Chung-Ming
    Kuo, Tai-Haur
    2019 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2019,
  • [35] A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation
    Kim, Jong-In
    Oh, Dong-Ryeol
    Jo, Dong-Shin
    Sung, Ba-Ro-Saim
    Ryu, Seung-Tak
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2015, 50 (10) : 2319 - 2330
  • [36] A 14b 80MS/s SAR ADC with 73.6dB SNDR in 65nm CMOS
    Kapusta, Ron
    Shen, Junhua
    Decker, Steven
    Li, Hongxing
    Ibaragi, Eitake
    2013 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC), 2013, 56 : 472 - U677
  • [37] A 9.15mW 0.22mm2 10b 204MS/s Pipelined SAR ADC in 65nm CMOS
    Jeon, Young-Deuk
    Cho, Young-Kyun
    Nam, Jae-Won
    Kim, Kwi-Dong
    Lee, Woo-Yol
    Hong, Kuk-Tae
    Kwon, Jong-Kee
    IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010, 2010,
  • [38] A 7.5-GS/s 3.8-ENOB 52-mW flash ADC with clock duty cycle control in 65nm CMOS
    Chung, Hayun
    Rylyakov, Alexander
    Deniz, Zeynep Toprak
    Bulzacchelli, John
    Wei, Gu-Yeon
    Friedman, Daniel
    2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2009, : 268 - +
  • [39] A 3-mW 12b 160-MS/s 2-Way Time-Interleaved Subrange SAR ADC in 65-nm CMOS
    Chung, Yung-Hui
    Rih, Wei-Shu
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2020, 67 (04) : 645 - 649
  • [40] A 12-bit 1.6 GS/s Interleaved SAR ADC with Dual Reference Shifting and Interpolation Achieving 17.8 fJ/conv-step in 65nm CMOS
    Nam, Jae-Won
    Hassanpourghadi, Mohsen
    Zhang, Aoyang
    Chen, Mike Shuo-Wei
    2016 IEEE SYMPOSIUM ON VLSI CIRCUITS (VLSI-CIRCUITS), 2016,