A 5.5mW 6b 5GS/s 4x-Interleaved 3b/cycle SAR ADC in 65nm CMOS

被引:0
|
作者
Chan, Chi-Hang [1 ]
Zhu, Yan [1 ]
Sin, Sai-Weng [1 ]
Seng-Pan, U. [1 ,2 ]
Martins, R. P. [1 ,3 ]
机构
[1] Univ Macau, Macau, Peoples R China
[2] Synopsys, Macau, Peoples R China
[3] Univ Lisbon, Inst Super Tecn, P-1699 Lisbon, Portugal
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:466 / +
页数:3
相关论文
共 50 条
  • [21] A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI
    Chen, Vanessa Hung-Chu
    Pileggi, Lawrence
    2014 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC), 2014, 57 : 380 - +
  • [22] A Background Calibrated 28GS/s 8b Interleaved SAR ADC in 28nm CMOS
    Le, M. Q.
    Gorecki, J.
    Riani, J.
    Pernillo, J.
    Tan, A.
    Gopalakrishnan, K.
    Helal, B.
    Khandelwal, P.
    Loi, C.
    Quek, I.
    Wong, P.
    Buchwald, A.
    2017 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2017,
  • [23] A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS
    Doris, Kostas
    Janssen, Erwin
    Nani, Claudio
    Zanikopoulos, Athon
    van der Weide, Gerard
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (12) : 2821 - 2833
  • [24] A 1.2V 30mW 8b 800MS/s time-interleaved ADC in 65nm CMOS
    Tu, Wei-Hsuan
    Kang, Tzung-Hung
    2008 IEEE SYMPOSIUM ON VLSI CIRCUITS, 2008, : 57 - 58
  • [25] A 1.2V 30mW 8b 800MS/s time-interleaved ADC in 65nm CMOS
    Tu, Wei-Hsuan
    Kang, Tzung-Hung
    2008 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2008, : 72 - 73
  • [26] A 6b 1.6GS/s ADC with Redundant Cycle 1-Tap Embedded DFE in 90nm CMOS
    Tabasy, E. Zhian
    Shafik, A.
    Huang, S.
    Yang, N.
    Hoyos, S.
    Palermo, S.
    2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2012,
  • [27] A 8-b 1GS/s 2b/cycle SAR ADC in 28-nm CMOS
    Ma, Song
    Liu, Liyuan
    Liu, Jian
    Wu, Nanjian
    2019 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2019), 2019, : 21 - 24
  • [28] A 2GS/s 8b Flash ADC Based on Remainder Number System in 65nm CMOS
    Zhu, Shuang
    Wu, Bo
    Cai, Yongda
    Chiu, Yun
    2017 SYMPOSIUM ON VLSI CIRCUITS, 2017, : C284 - C285
  • [29] A 6b 1GS/s 2b/Cycle SAR ADC with Body-Voltage Offset Calibration
    Chen, Hsin-Shu
    Huang, Sheng-Hsiang
    Tai, Hung-Yen
    Lin, Sen-Wei
    Wu, Shi-Wei
    2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2020,
  • [30] A 5GS/s 158.6mW 12b Passive-Sampling 8x-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS
    Ramkaj, Athanasios
    Ramos, Juan Carlos Pena
    Lyu, Yifan
    Strackx, Maarten
    Pelgrom, Marcel J. M.
    Steyaert, Michiel
    Verhelst, Marian
    Tavernier, Filip
    2019 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2019, 62 : 62 - +