Model-Based Actor Multiplexing with Application to Complex Communication Protocols

被引:0
作者
Zebelein, Christian [1 ]
Haubelt, Christian [1 ]
Falk, Joachim [2 ]
Schwarzer, Tobias [2 ]
Teich, Juregen [2 ]
机构
[1] Univ Rostock, D-18055 Rostock, Germany
[2] Univ Erlangen Nurnberg, Nurnberg, Germany
来源
2014 DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION (DATE) | 2014年
关键词
EXPLORATION;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
We propose a dynamic scheduling approach for the concurrent execution of logical actor instances on a single synthesized actor instance. Based on a formal dataflow model of computation, the proposed approach can be applied to a wide range of applications in a model-based design flow. As case-study, we evaluate a bus-cycle-accurate SystemC RTL model based on an InfiniBand network adapter in a PCI Express system.
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页数:4
相关论文
共 11 条
[1]  
Gerstlauer A, 2012, ASIA S PACIF DES AUT, P213, DOI 10.1109/ASPDAC.2012.6164947
[2]  
Grotker T., 2002, SYSTEM DESIGN SYSTEM
[3]   Exploring the Concurrency of an MPEG RVC Decoder Based on Dataflow Program Analysis [J].
Gu, Ruirui ;
Janneck, Joern W. ;
Bhattacharyya, Shuvra S. ;
Raulet, Mickael ;
Wipliez, Matthieu ;
Plishker, William .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 2009, 19 (11) :1646-1657
[4]  
ITA, 2013, INFINIBANS SPEC
[5]   Resource constrained modulo scheduling with global resource sharing [J].
Jäschke, C ;
Laur, R .
11TH INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS - PROCEEDINGS, 1998, :60-65
[6]   SYSTEMCODESIGNER-An Automatic ESL Synthesis Approach by Design Space Exploration and Behavioral Synthesis for Streaming Applications [J].
Keinert, Joachim ;
Streubuhr, Martin ;
Schlichter, Thomas ;
Falk, Joachim ;
Gladigau, Jens ;
Haubelt, Christian ;
Teich, Jurgen ;
Meredith, Michael .
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2009, 14 (01)
[7]   STATIC SCHEDULING OF SYNCHRONOUS DATA FLOW PROGRAMS FOR DIGITAL SIGNAL-PROCESSING [J].
LEE, EA ;
MESSERSCHMITT, DG .
IEEE TRANSACTIONS ON COMPUTERS, 1987, 36 (01) :24-35
[8]  
Meeus W., 2013, OVERVIEW TODAYS HIGH
[9]   FPGA pipeline synthesis design exploration using module selection and resource sharing [J].
Sun, Welson ;
Wirthlin, Michael J. ;
Neuendorffer, Stephen .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2007, 26 (02) :254-265
[10]  
Zebelein C., 2013, P FDL