A 2.5-Gb/s half-rate clock and data recovery circuit with a digital quadricorrelator frequency detector

被引：1

作者：

Tang Shimin ^{[1
,2
]}

Chen Jihua ^{[2
]}

Chen Nuxing ^{[2
]}

Feng Yingjie ^{[2
]}

机构：

[1] Inst Southwest Elect & Telecom, Chengdu 610041, Peoples R China

[2] Natl Univ Def Technol, Inst Microelect & MicroPro, Sch Comp, Changsha 410073, Peoples R China

来源：

ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2007年

关键词：

CDR; half-rate; linear phase detector; DQFD; VCO;

D O I：

10.1109/ICASIC.2007.4415703

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 2.5-Gb/s clock and data recovery (CDR) circuit, which incorporates dual loop architecture with half-rate linear phase detector and digital quadricorrelator frequency detector (DQFD) was present in this paper. The circuit is implemented under 0.13 mu m CMOS process with the core chip area of 350 mu m* 110 mu m. The hspice simulation results show that the center frequency of the voltage-controlled oscillator (VCO) is 1.25GHz, the lock time is less than 5 mu s, the operation range is from 2.20Gbps to 2.83Gbps, and the power consumption is about 15.2mW at supply voltage of 1.2v.

引用

页码：604 / 607

页数：4

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