A 64GHz 6.5 dB NF 15.5 dB gain LNA in 90nm CMOS

被引:16
作者
Pellerano, Stefano [1 ]
Palaskas, Yorgos [1 ]
Soumyanath, Krishnamurthy [1 ]
机构
[1] Intel Corp, Communicat Circuits Lab, Hillsboro, OR 97124 USA
来源
ESSCIRC 2007: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2007年
关键词
D O I
10.1109/ESSCIRC.2007.4430316
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents an integrated LNA for mm-wave applications implemented in 90nm CMOS technology. Modeling methodology based solely on electromagnetic simulations, RC parasitic extraction and device measurements up to 20GHz allows for "correct-by-construction" design at mm-wave frequency and first-pass silicon success. The dual-stage cascode LNA has a peak gain of 15.5dB at 64GHz with an NF of 6.5dB, while drawing 26mA per stage from 1.65V. Output P-1dB is 3.8dBm. At V-DD = 1.26V, each stage draws 19mA, with a peak gain and a NF of 13.5dB and 6.7dB respectively. To the authors' knowledge, this is the lowest measured NF at mm-wave frequencies reported so far in CMOS. Measured results are in excellent agreement with simulations. A custom set-up for mm-wave NF measurement is also extensively described in the paper.
引用
收藏
页码:352 / 355
页数:4
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