A hardware/software co-design vs. hardware implementation of the modular exponentiation using the sliding-window method with constant-length partitioning

Modular exponentiation is a basic operation in cryptosystems. Generally, the performance of this operation has a tremendous impact on the efficiency of the whole application. The efficiency of the modular exponentiation, in turn, depends mainly on that of modular multiplications as the former is somehow a repetition of the latter. One of the methods that computes the modular power is the sliding-window method, which preprocesses the exponent into zero and non-zero partitions. Zero partitions allow for a reduction of the number of modular multiplications required in the exponentiation process. In this paper, we devise a novel system-on-chip (SoC) implementation for computing modular exponentiation using the sliding-window method. We also propose a hardware-only implementation for that operation. The partitioning strategy used in both approaches allows constant-length non-zero partitions, which increases the average number of zero partitions and so decreases that of non-zero partitions. The partitioning strategy allows variable-length zero partitions. The hardware/software co-design implements the modular multiplication on hardware and the rest of the system in software. We provide a useful comparison of the SoC-based implementation against hardware-only implementation. Both of the proposed implementations can be used in any industrial embedded system that needs to secure the handled information.