Hardware implementation of a novel edge-map generation technique for pupil detection in NIR images

被引:10
作者
Kumar, Vineet [1 ]
Asati, Abhijit [1 ]
Gupta, Anu [1 ]
机构
[1] Birla Inst Technol & Sci Pilani, Dept Elect & Elect Engn, Pilani 333031, Rajasthan, India
来源
ENGINEERING SCIENCE AND TECHNOLOGY-AN INTERNATIONAL JOURNAL-JESTECH | 2017年 / 20卷 / 02期
关键词
Iris localization; Pupil detection; Edge-map generation; FPGA based implementation; Hardware implementation; IRIS RECOGNITION; HOUGH TRANSFORM; LOCALIZATION; SEGMENTATION; ARCHITECTURE; BIOMETRICS; SYSTEMS; DESIGN;
D O I
10.1016/j.jestch.2016.11.001
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
This paper proposes an edge-map generation technique for pupil detection in near infrared (NIR) images and its hardware implementation. The proposed edge-map generation technique is based on generating two different edge-maps of same eye image using Gaussian filtering, image binarization and Sobel edge detection operations and then combining them to a single edge-map using intersection operation on binary images. This technique reduces the false edges drastically in the edge-map of eye image, which is desirable for accurate and fast pupil detection. Field programmable logic array (FPGA) based hardware implementation of the proposed technique is presented, which can be used in iris localization system on FPGA based platforms for iris recognition application. The proposed edge-map generation hardware is a parallel-pipelined implementation. (C) 2016 Karabuk University. Publishing services by Elsevier B.V.
引用
收藏
页码:694 / 704
页数:11
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