Glitch Elimination and Optimization of Dynamic Power Dissipation in Combinational Circuits

被引：0

作者：

Karthik, H. S. ^{[1
]}

Naik, B. Mohan Kumar ^{[2
]}

机构：

[1] APS Coll Engn, Dept Elect & Commun Engn, Bangalore, Karnataka, India

[2] New Horizon Coll Engn, Dept Elect & Commun Engn, Bangalore, Karnataka, India

来源：

2014 INTERNATIONAL CONFERENCE ON ADVANCES IN ELECTRONICS, COMPUTERS AND COMMUNICATIONS (ICAECC) | 2014年

关键词：

Low power; Dynamic Power Dissipation; Glitch; Switching Activity; Glitch Width; Propagation delay; Transmission Gate;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Low power consumption has become a highly important concern for the designs. Glitches contribute to the dynamic power which itself is a major portion of the total power consumed by designs. A glitch is an undesired transition that occurs before intended value in digital circuits. A glitch occurs in CMOS circuits due to differential delay at the inputs of a gate. The paper describes a procedure to estimate and optimize dynamic power dissipation for combinational circuits due to propagation delay. First, cause of glitch and power dissipated due to presence of it is estimated. Secondly, a technique using transmission gate is employed and the glitch is eliminated. Then a comparison of the power dissipated is carried out to know the optimized power for 1.2um and 0.8um CMOS Technologies.

引用

页数：6

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