Annealing process influence and dopant-silicide interaction in self-aligned NiSi technology

被引:0
作者
Ru, GP [1 ]
Jiang, YL [1 ]
Qu, XP [1 ]
Li, BZ [1 ]
机构
[1] Fudan Univ, Dept Microelect, Shanghai 200433, Peoples R China
来源
2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS | 2004年
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper reports the annealing process influence on interfacial electrical properties, dopant effects on silicide formation, and dopant redistribution during silicidation in self-aligned NiSi technology. The reverse leakage Current results of NiSi/n-Si Schottky diodes show that two-step rapid thermal process (RTP) significantly improves the NiSi/Si area-contact characteristics in comparison with one-step RTP. and low temperature in RTP1 is beneficial to the final Ni-silicide/Si contact properties. Both structural and electrical characterization shows substantially different Ni-silicidation behaviors on heavily-doped n(+) and p(+) Si substrates at low temperature (300 degrees C). The larger grain size of Ni2Si formed on heavily As-doped Si is responsible for the lower resistivity, comparing with Ni2Si formed on heavily B-doped Si. Ni/Si reaction on highly doped Si substrates also results in significant dopant segregation at the silicide/Si interface and pile up in void-layer formed just underneath the silicide surface.
引用
收藏
页码:451 / 455
页数:5
相关论文
共 12 条
[1]   Silicides and ohmic contacts [J].
Gambino, JP ;
Colgan, EG .
MATERIALS CHEMISTRY AND PHYSICS, 1998, 52 (02) :99-146
[2]   NiSi salicide technology for scaled CMOS [J].
Iwai, H ;
Ohguro, T ;
Ohmi, S .
MICROELECTRONIC ENGINEERING, 2002, 60 (1-2) :157-169
[3]  
JIANG YH, UNPUB, P12720
[4]  
JIANG YL, IN PRESS APPL PHYS L, V85
[5]   Materials aspects, electrical performance, and scalability of Ni silicide towards sub-0.13 μm technologies [J].
Lauwers, A ;
Steegen, A ;
de Potter, M ;
Lindsay, R ;
Satta, A ;
Bender, H ;
Maex, K .
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2001, 19 (06) :2026-2037
[6]  
Lu JP, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P371, DOI 10.1109/IEDM.2002.1175855
[7]  
LU JP, 2004, ADV SHORT TIME THERM, V2, P159
[8]   SELF-ALIGNED NICKEL-MONO-SILICIDE TECHNOLOGY FOR HIGH-SPEED DEEP-SUBMICROMETER LOGIC CMOS ULSI [J].
MORIMOTO, T ;
OHGURO, T ;
MOMOSE, HS ;
IINUMA, T ;
KUNISHIMA, I ;
SUGURO, K ;
KATAKABE, I ;
NAKAJIMA, H ;
TSUCHIAKI, M ;
ONO, M ;
KATSUMATA, Y ;
IWAI, H .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1995, 42 (05) :915-922
[9]  
SMIGELSKAS AD, 1947, T AM I MIN MET ENG, V171, P130
[10]   ON THE DIFFERENCE IN APPARENT BARRIER HEIGHT AS OBTAINED FROM CAPACITANCE-VOLTAGE AND CURRENT-VOLTAGE-TEMPERATURE MEASUREMENTS ON AL/P-INP SCHOTTKY BARRIERS [J].
SONG, YP ;
VANMEIRHAEGHE, RL ;
LAFLERE, WH ;
CARDON, F .
SOLID-STATE ELECTRONICS, 1986, 29 (06) :633-638