Re-using clock management unit to implement power Gating and retention for leakage reduction at the 65-nm technology node

被引：0

作者：

Royannez, P. ^{[1
]}

Jumel, F. ^{[1
]}

Mair, H. ^{[1
]}

Scott, D. ^{[1
]}

Rachidi, A. Er ^{[1
]}

Lagerquist, R. ^{[1
]}

Chau, M. ^{[1
]}

Gururajarao, S. ^{[1
]}

Thiruvengadam, S. ^{[1
]}

Clinton, M. ^{[1
]}

Menezes, V. ^{[1
]}

Hollingsworth, R. ^{[1
]}

Vaccani, J. ^{[1
]}

Piacibello, F. ^{[1
]}

Culp, N. ^{[1
]}

Rosal, J. ^{[1
]}

Ball, M. ^{[1
]}

Ben-Amar, F. ^{[1
]}

Bouetel, L. ^{[1
]}

Domerego, O. ^{[1
]}

Lachese, J. L. ^{[1
]}

Fournet-Fayard, C. ^{[1
]}

Ciroux, J. ^{[1
]}

Raibaut, C. ^{[1
]}

Ko, U. ^{[1
]}

机构：

[1] Texas Instruments Inc, 821 Ave Jack Kilby,BP 5, F-06270 Villeneuve Loubet, France

来源：

2007 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS | 2007年

关键词：

leakage power management; wireless SoC;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Leakage power management, wireless SoC In this paper we present a leakage management system which takes advantage of the existing clock gating infrastructure. This methodology avoids both RTL and software changes, at the block and chip level. We illustrate this approach with a 65-nm digital base band modem while achieving standby leakage in the 100-uA range and overall 1200X leakage reduction including process, circuit and system optimization.

引用

页码：37 / +

页数：2