A 9-bit, 14 μW and 0.06 mm2 Pulse Position Modulation ADC in 90 nm Digital CMOS

被引：66

作者：

Naraghi, Shahrzad ^{[1
,2
]}

Courcy, Matthew ^{[3
]}

Flynn, Michael P. ^{[2
]}

机构：

[1] Cirrus Log Inc, Austin, TX 78746 USA

[2] Univ Michigan, Ann Arbor, MI 48109 USA

[3] Natl Semicond Corp, Salem, NH 03079 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2010年 / 45卷 / 09期

关键词：

ADC; PPM; TDC; CONVERTER; NOISE;

D O I：

10.1109/JSSC.2010.2050945

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work presents a compact, low-power, time-based architecture for nanometer-scale CMOS analog-to-digital conversion. A pulse position modulation ADC architecture is proposed and a prototype 9 bit PPM ADC incorporating a two-step TDC scheme is presented as proof of concept. The 0.06 mm(2) prototype is implemented in 90 nm CMOS and achieves 7.9 effective bits across the entire input bandwidth and dissipates 14 mu W at 1 MS/s.

引用

页码：1870 / 1880

页数：11

共 33 条

[1] Phase noise and jitter in CMOS ring oscillators [J].

Abidi, Asad A. .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (08) :1803-1816

[2]

AKOPYAN F, P 12 IEEE INT S AS C

[3] New class of asynchronous A/D converters based on time quantization [J].

Allier, E ;

Sicard, G ;

Fesquet, L ;

Renaudin, M .

NINTH INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS, PROCEEDINGS, 2003, :196-205

[4]

ALLIER E, 2005, ISLPED O5 AUG

[5] A PVT insensitive vernier-based time-to-digital converter with extended input range and high accuracy [J].

Chen, Poki ;

Chen, Chun-Chi ;

Zheng, Jia-Chi ;

Shen, You-Sheng .

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2007, 54 (02) :294-302

[6] An integrated high resolution CMOS timing generator based on an array of delay locked loops [J].

Christiansen, J .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (07) :952-957

[7] A low power multi-channel single ramp ADC with up to 3.2 GHz virtual clock [J].

Delagnes, Eric ;

Breton, Dominique ;

Lugiez, Francis ;

Rahmanifard, Reza .

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2007, 54 (05) :1735-1742

[8] A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line [J].

Dudek, P ;

Szczepanski, S ;

Hatfield, JV .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (02) :240-247

[9]

FUSAYASU T, 2007, NUCL SCI S C REC OCT, V1, P302

[10]

HANZLER S, 2008, IEEE ISSCC FEB, P548

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