2-4 and 9-12 Gb/s CMOS Fully Integrated ILO-based CDR

被引：7
作者：
Mazouffre, O. [1 ]
Toupe, R. [1 ]
Pignol, M. [2 ]
Deval, Y. [1 ]
Begueret, J. B. [1 ]
机构：
[1] Univ Bordeaux, IMS Lab, Talence, France
[2] CNES, Toulouse, France
来源：
2010 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS RFIC SYMPOSIUM | 2010年
关键词：
Clock and data recovery circuit; CDR; Injection Locked Oscillator; ILO; Satellite; CMOS; gigabit; INJECTION-LOCKED OSCILLATOR;
D O I：
10.1109/RFIC.2010.5477391
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A CDR dedicated to satellite data link is presented. The clock recovery function is made-up of an Injection Locked Oscillator combined with an analog phase alignment circuit. The circuit covers two bit-rate ranges: 2.2 to 4.3 Gb/s and 9.1 to 12.1 Gb/s. It was designed in 130 nm CMOS bulk process from STMicroelectronics. The overall power dissipation is 400 mW in the first bit-rate range and 480 mW in the second including 220 mW for I/O buffers. The eye opening at 10(-9) of bit error rate is 940 mUI/440 mV at 3.1 Gb/s and 720 mUI/300 mV at 10.3 Gb/s.
引用
收藏
页码：553 / 556
页数：4
相关论文
共 9 条
[1]   An innovative open-loop CDR based on injection-locked oscillator for high-speed data link applications [J].
Bégueret, JB ;
Deval, Y ;
Scarabello, C ;
Le Gall, JY ;
Pignol, M .
2003 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS, 2003, :313-316
[2]   Effects of technology scaling on the SET sensitivity of RF CMOS voltage-controlled oscillators [J].
Boulghassoul, Y ;
Massengill, LW ;
Sternberg, AL ;
Bhuva, BL .
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2005, 52 (06) :2426-2432
[3]   A heavy-ion tolerant clock and data recovery circuit for satellite embedded high-speed data links [J].
Lapuyade, H. ;
Mazouffre, O. ;
Goumballa, B. ;
Pignol, M. ;
Malou, F. ;
Neveu, C. ;
Pouget, V. ;
Deval, Y. ;
Begueret, J. B. .
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2007, 54 (06) :2080-2085
[4]   A radiation-hardened injection locked oscillator devoted to radio-frequency applications [J].
Lapuyade, H. ;
Pouget, V. ;
Begueret, J. B. ;
Hellmuth, P. ;
Taris, T. ;
Mazouffre, O. ;
Fouillat, R. ;
Deval, Y. .
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2006, 53 (04) :2040-2046
[5]  
Lee JS, 2007, IEEE IND ELEC, P46
[6]   A fully on-chip 10Gb/s CDR in a standard 0.18 μm CMOS technology [J].
Li, Jinghua ;
Silva-Martinez, Jose .
2007 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS, 2007, :237-+
[7]  
MAZOUFFRE, 2007, ESSCIRC, P520
[8]  
MING Z, 2005, P IEEE INT REL PHYS, P223
[9]   A 12.5Gbps half-rate CMOS CDR circuit for 10Gbps network applications [J].
Takasoh, J ;
Yoshimura, T ;
Kondoh, H ;
Higashisaka, N .
2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2004, :268-271
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