Scaling issues in lateral power MOSFETs

被引：21

作者：

Darwish, M ^{[1
]}

Huang, J ^{[1
]}

Liu, MX ^{[1
]}

Shekar, MS ^{[1
]}

Williams, R ^{[1
]}

Cornell, M ^{[1
]}

机构：

[1] Siliconix, Santa Clara, CA 95056 USA

来源：

ISPSD '98 - PROCEEDINGS OF THE 10TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS | 1998年

关键词：

D O I：

10.1109/ISPSD.1998.702701

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The interconnect limitations and scaling issues for large area lateral al multi-cell power MOS transistors, as they approach the ULSI realm, are investigated. The increased importance of scaling metal pitch and number of layers for different MOS technologies is discussed. Furthermore, voltage drop and current distribution along metal runners for different examples of layout options are examined in order to gain insight into seating and layout considerations. It is shown that temperature behavior of devices with different metal length can be used to extract the contribution of metal interconnect from measured data.

引用

页码：329 / 332

页数：4