Poly-Si-gate-related variability in decananometer MOSFETs with conventional architecture

被引：76

作者：

Brown, Andrew R. ^{[1
]}

Roy, Gareth ^{[1
]}

Asenov, Asen ^{[1
]}

机构：

[1] Univ Glasgow, Device Modelling Grp, Dept Elect & Elect Engn, Glasgow G12 8LT, Lanark, Scotland

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2007年 / 54卷 / 11期

基金：

英国工程与自然科学研究理事会;

关键词：

fermi-level pinning; MOSFETs; polysilicon (poly-Si) grain boundaries; variability;

D O I：

10.1109/TED.2007.907802

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we present a comprehensive statistical 3-D simulation study of the effect of polysilicon (poly-Si) gate granularity on the threshold voltage variability in decananometer MOSFETs with conventional (bulk) architecture. Initially, the effect of both the pinning of the Fermi level. and the doping nominiformity at the poly-Si grain boundaries are studied and compared considering a single grain boundary crossing through the middle of the channel for different pinning positions and doping concentrations at the boundary. This is followed by systematic simulation results for the impact of the grain-size distribution on the standard deviation of the threshold voltage in a simple 30 x 30 nm MOSFET with uniform channel doping for different pinning positions and doping levels at the grain boundaries. Finally, simulation results for the magnitude of the threshold voltage variations induced by the poly-Si granularity are presented for a set of carefully scaled "realistic" bulk MOSFETs with gate lengths of 35, 25, 18, 13, and 9 nm and are compared with the variations introduced by random discrete dopants and line-edge roughness.

引用

页码：3056 / 3063

页数：8

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