Architecting Large-Scale SRAM Arrays with Monolithic 3D Integration

被引：0

作者：

Kong, Joonho ^{[1
]}

Gong, Young-Ho ^{[2
]}

Chung, Sung Woo ^{[2
]}

机构：

[1] Kyungpook Natl Univ, Sch Elect Engn, Daegu, South Korea

[2] Korea Univ, Dept Comp Sci & Engn, Seoul, South Korea

来源：

2017 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED) | 2017年

基金：

新加坡国家研究基金会;

关键词：

Monolithic 3D Integrations; Last-Level Caches; Performance; Energy;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we architect large-scale SRAM arrays with monolithic 3D (M3D) integration technology. We introduce M3D-based SRAM arrays with three different ways of integration: M3D-R (vertical routing-only), M3D-VBL (vertical bitline), and M3D-VWL (vertical wordline). We also apply M3D-based SRAM arrays to last-level caches: tag arrays for eDRAM LLCs and data arrays for SRAM LLCs. The proposed LLCs with M3Dbased SRAM arrays lead to better performance and lower energy by 0.02%similar to 1.7% and 49.1%similar to 79.1%, respectively, compared to that with TSV-based 3D SRAM arrays. I

引用

页数：6