Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology

被引:6
作者
Garghetti, Alessandro [1 ]
Lacaita, Andrea L. [2 ]
Seebacher, David [1 ]
Bassi, Matteo [1 ]
Levantino, Salvatore [2 ]
机构
[1] Infineon Technol Austria AG, A-9500 Villach, Austria
[2] Politecn Milan, Dipartimento Elettron Informaz & Bioingn, I-20133 Milan, Italy
关键词
Frequency conversion; Oscillators; Power demand; Harmonic analysis; Frequency synthesizers; Voltage; Topology; CMOS; divide-by-five; frequency synthesis; inductor-less; injection-locked frequency divider (ILFD); locking range; low power; millimeter-wave (mm-wave); phase-locked loop (PLL); radio frequency (RF); ring oscillator; LOCKING;
D O I
10.1109/JSSC.2021.3134486
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Based on a detailed analysis of harmonic generation in ring-based injection-locked frequency dividers (ILFDs), this article shows that concurrent injection signals can be generated in these stages by driving both tail and direct injectors with the same input signal. Based on this result, a novel ring-based divide-by-five ILFD is presented, where multi-injection is reinforced by a dual-path scheme, largely broadening the locking range with no penalty in power dissipation. The stage, implemented in a 28-nm CMOS process, operates over the 8-to-101.6-GHz frequency range achieving a >20% locking over the 13.6-69.1-GHz interval, with 5.6-mW maximum power consumption from a 0.9-V supply. The stage also achieves 101.6 GHz, the highest operating frequency among state-of-the-art CMOS ILFDs by five, with 2.6% locking range.
引用
收藏
页码:1788 / 1799
页数:12
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