Tree Multipliers with Modified Booth Algorithm Based on Adiabatic CPL

This paper describes an adiabatic tree multiplier based on modified Booth algorithm, which operates on four-phase power clocks. It is composed of Booth encoder, partial product generators followed by booth encoding, a complementary decoder that is required by the partial product generator, Wallace trees with 4-2 compressors, and a fmal carry-lookahead adder. All circuits are realized by CPAL (Complementary Pass-transistor Adiabatic Logic) circuits with TSMC 0.18 mu m CMOS process technology. Compared with its CMOS counterpart based on conventional logic circuits, the four-phase adiabatic multiplier attains energy savings of 86.6% at 50MHz and 72.8% at 300MHz, respectively.