A compact model of the pinch-off region of 100 nm MOSFETs based on the surface-potential

被引：2

作者：

Navaro, D ^{[1
]}

Mizoguchi, T

Suetake, M

Hisamitsu, K

Ueno, H

Miura-Mattausch, M

Mattausch, HJ

Kumashiro, S

Yamaguchi, T

Yamashita, K

Nakayama, N

机构：

[1] Hiroshima Univ, Grad Sch Adv Sci Matter, Higashihiroshima 7398530, Japan

[2] Hiroshima Univ, Res Ctr Nanodevices & Syst, Higashihiroshima 7398526, Japan

[3] Semicond Technol Acad Res Ctr, Yokohama, Kanagawa 2220033, Japan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2005年 / E88C卷 / 05期

关键词：

pinch-off region; channel-length modulation; overlap capacitance; surface-potential-based modeling; circuit simulation;

D O I：

10.1093/ietele/e88-c.5.1079

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have developed a model for circuit-simulation which describes the MOSFET region from pinch-off to drain contact based on the surface potential. The model relates the surface-potential increase beyond the pinch-off point to the channel/drain junction profile by applying the Gauss law with the assumption that the lateral field is greater than the vertical one. Explicit equations for the lateral field and the pinch-off length are obtained, which take the potential increase in the drain overlap region into account. The model, as implemented into a circuit simulator, correctly reproduces measured channel conductance and overlap capacitance for 100 nm pocket-implant technologies as a function of bias condition and gate length.

引用

页码：1079 / 1086

页数：8

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