Scalable Digital Neuromorphic Architecture for Large-Scale Biophysically Meaningful Neural Network With Multi-Compartment Neurons

被引:257
作者
Yang, Shuangming [1 ]
Deng, Bin [1 ]
Wang, Jiang [1 ]
Li, Huiyan [2 ]
Lu, Meili [3 ]
Che, Yanqiu [4 ]
Wei, Xile [1 ]
Loparo, Kenneth A. [5 ]
机构
[1] Tianjin Univ, Sch Elect & Informat Engn, Tianjin 300072, Peoples R China
[2] Tianjin Univ Technol & Educ, Sch Automat & Elect Engn, Tianjin 300222, Peoples R China
[3] Tianjin Univ Technol & Educ, Sch Informat Technol Engn, Tianjin 300222, Peoples R China
[4] Penn State Coll Med, Dept Neurosurg, Hershey, PA 17033 USA
[5] Case Western Reserve Univ, Dept Elect Engn & Comp Sci, Cleveland, OH 44106 USA
基金
中国国家自然科学基金;
关键词
Neurons; Computational modeling; Neuromorphics; Biological system modeling; Brain modeling; Hardware; Biological neural networks; Compartmental neuron (CMN) model; field-programmable gate array (FPGA); network on chip (NoC); neuromorphic engineering; spiking neural network (SNN); MULTIPLIERLESS IMPLEMENTATION; MODEL; DYNAMICS; COMMUNICATION; INTEGRATION; FREQUENCY; SYSTEM; FPGA;
D O I
10.1109/TNNLS.2019.2899936
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Multicompartment emulation is an essential step to enhance the biological realism of neuromorphic systems and to further understand the computational power of neurons. In this paper, we present a hardware efficient, scalable, and real-time computing strategy for the implementation of large-scale biologically meaningful neural networks with one million multi-compartment neurons (CMNs). The hardware platform uses four Altera Stratix III field-programmable gate arrays, and both the cellular and the network levels are considered, which provides an efficient implementation of a large-scale spiking neural network with biophysically plausible dynamics. At the cellular level, a cost-efficient multi-CMN model is presented, which can reproduce the detailed neuronal dynamics with representative neuronal morphology. A set of efficient neuromorphic techniques for single-CMN implementation are presented with all the hardware cost of memory and multiplier resources removed and with hardware performance of computational speed enhanced by 56.59% in comparison with the classical digital implementation method. At the network level, a scalable network-on-chip (NoC) architecture is proposed with a novel routing algorithm to enhance the NoC performance including throughput and computational latency, leading to higher computational efficiency and capability in comparison with state-of-the-art projects. The experimental results demonstrate that the proposed work can provide an efficient model and architecture for large-scale biologically meaningful networks, while the hardware synthesis results demonstrate low area utilization and high computational speed that supports the scalability of the approach.
引用
收藏
页码:148 / 162
页数:15
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