Constraint-Aware Algorithms for Heterogeneous Power Module Layout Synthesis and Reliability Optimization

被引：0

作者：

Al Razi, Imam ^{[1
]}

Le, Quang ^{[2
]}

Mantooth, H. Alan ^{[2
]}

Peng, Yarui ^{[1
]}

机构：

[1] Univ Arkansas, Comp Sci & Comp Engn Dept, Fayetteville, AR 72701 USA

[2] Univ Arkansas, Elect Engn Dept, Fayetteville, AR 72701 USA

来源：

2018 IEEE 6TH WORKSHOP ON WIDE BANDGAP POWER DEVICES AND APPLICATIONS (WIPDA) | 2018年

基金：

美国国家科学基金会;

关键词：

PowerSynth; corner stitch; constraint graph; Multi-Chip Power Module; algorithms; layout optimization;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A constraint-aware layout engine is developed for PowerSynth to explore heterogeneous power module layout synthesis and optimization considering reliability. For this purpose, the corner stitching data structure with constraint graph evaluation is extended for power module layouts with generic, scalable, and efficient algorithms to place and route heterogeneous components including active devices, sensors, controllers, and other passive components. Unlike VLSI, in power modules design, layout compaction is not the optimum target because of thermal and reliability issues associated with high voltage and current. Therefore, in this layout engine, both design and reliability constraints are honored while generating layout solutions by evaluating constraint graphs and randomizing edge weights. Compared with existing work, the proposed algorithms can process a broader range of layouts with a higher geometrical complexity within a few minutes. In addition, the produced layouts are both reliable and design-rule-check (DRC)-clean, which improves both time complexity and layout quality.

引用

页码：323 / 330

页数：8

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