NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps

被引:187
作者
Aimar, Alessandro [1 ,2 ]
Mostafa, Hesham [1 ,2 ,3 ]
Calabrese, Enrico [1 ,2 ]
Rios-Navarro, Antonio [4 ]
Tapiador-Morales, Ricardo [4 ]
Lungu, Iulia-Alexandra [1 ,2 ]
Milde, Moritz B. [1 ,2 ]
Corradi, Federico [5 ,6 ]
Linares-Barranco, Alejandro [4 ]
Liu, Shih-Chii [1 ,2 ]
Delbruck, Tobi [1 ,2 ]
机构
[1] Univ Zurich, Inst Neuroinformat, CH-8057 Zurich, Switzerland
[2] Swiss Fed Inst Technol, CH-8057 Zurich, Switzerland
[3] Univ Calif San Diego, Inst Neural Computat, La Jolla, CA 92093 USA
[4] Univ Seville, Robot & Technol Comp Lab, E-41012 Seville, Spain
[5] IniLabs GmbH, CH-8001 Zurich, Switzerland
[6] IMEC Netherlands, NL-5656 AE Eindhoven, Netherlands
关键词
Artificial intelligence; computer vision; convolutional neural networks (CNNs); field-programmable gate array (FPGA); VLSI;
D O I
10.1109/TNNLS.2018.2852335
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Convolutional neural networks (CNNs) have become the dominant neural network architecture for solving many state-of-the-art (SOA) visual processing tasks. Even though graphical processing units are most often used in training and deploying CNNs, their power efficiency is less than 10 GOp/s/W for single-frame runtime inference. We propose a flexible and efficient CNN accelerator architecture called NullHop that implements SOA CNNs useful for low-power and low-latency application scenarios. NullHop exploits the sparsity of neuron activations in CNNs to accelerate the computation and reduce memory requirements. The flexible architecture allows high utilization of available computing resources across kernel sizes ranging from 1x1 to 7x7. NullHop can process up to 128 input and 128 output feature maps per layer in a single pass. We implemented the proposed architecture on a Xilinx Zynq field-programmable gate array (FPGA) platform and presented the results showing how our implementation reduces external memory transfers and compute time in five different CNNs ranging from small ones up to the widely known large VGG16 and VGG19 CNNs. Postsynthesis simulations using Mentor Modelsim in a 28-nm process with a clock frequency of 500 MHz show that the VGG19 network achieves over 450 GOp/s. By exploiting sparsity, NullHop achieves an efficiency of 368%, maintains over 98% utilization of the multiply-accumulate units, and achieves a power efficiency of over 3 TOp/s/W in a core area of 6.3 mm(2). As further proof of NullHop's usability, we interfaced its FPGA implementation with a neuromorphic event camera for real-time interactive demonstrations.
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页码:644 / 656
页数:13
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