Tunneling Field Effect Transistors for Enhancing Energy Efficiency and Hardware Security of IoT Platforms: Challenges and Opportunities

被引：5

作者：

Aditya, Japa ^{[1
]}

Nagateja, T. ^{[1
]}

Vishvakarma, Santosh Kumar ^{[2
]}

Yellappa, Palagani ^{[3
]}

Choi, Jun Rim ^{[3
]}

Vaddi, Ramesh ^{[1
]}

机构：

[1] DSPM Int Inst Informat Technol, Nano Scale Integrated Circuits & Syst Self Powere, Elect & Commun Engn, Naya Raipur 49366, Chhattishgarh, India

[2] Indian Inst Technol Indore, Nanoscale Devices, VLSI Circuit & Syst Design Lab, Discipline Elect Engn, Indore 453552, Madhya Pradesh, India

[3] Kyungpook Natl Univ, Sch Elect Engn, Coll IT Engn, Daegu 702701, South Korea

来源：

2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2018年

关键词：

Tunnel FET; IoT; Ambipolarity; TRNG; 3D IC; DLDO; DESIGN;

D O I：

10.1109/ISCAS.2018.8350939

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Tunneling Field-Effect Transistor (TFET) is a leading future transistor option for next generation VLSI applications and Internet of things (IoT). Many have demonstrated the energy efficiency of TFET circuits. In this work, we demonstrate for the first time utilizing TFET ambipolar device characteristics for jitter generation in post-processing circuits of true random number generators (TRNGs) and suitability for enhancing hardware security of IoT platforms. Device and circuit design challenges for TFET based transceiver designs for capacitive coupled interconnect in 3DIC and on-chip low dropout digital voltage regulators (DLDOs) are further explored towards energy efficient IoT platforms.

引用

页数：5

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