Low Latency GF(2m) Polynomial Basis Multiplier

被引:12
作者
Luis Imana, Jose [1 ]
机构
[1] Univ Complutense, Dept Comp Architecture & Syst Engn, Fac Phys, E-28040 Madrid, Spain
关键词
Finite fields; implementation; multiplication; polynomial basis; VLSI; PARALLEL SYSTOLIC MULTIPLIER; FINITE-FIELD MULTIPLIERS; IRREDUCIBLE TRINOMIALS; ARCHITECTURES;
D O I
10.1109/TCSI.2010.2089553
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Finite field GF(2(m)) arithmetic is becoming increasingly important for a variety of different applications including cryptography, coding theory and computer algebra. Among finite field arithmetic operations, GF(2(m)) multiplication is of special interest because it is considered the most important building block. This contribution describes a new low latency parallel-in/ parallel-out sequential polynomial basis multiplier over GF(2(m)). For irreducible GF(2(m)) generating polynomials f(x) = x(m) + x(kt) + x(kt-1) + ... + x(k1) +1 with m >= 2k(t) - 1, the proposed multiplier has a theoretical latency of 2k(t) + 1 cycles. This latency is the lowest one found in the literature for GF(2(m)) multipliers. Furthermore, the condition m >= 2k(t) - 1 is specially important because the five binary irreducible polynomials recommended by NIST for elliptic curve cryptography ( ECC) implementation verify this condition.
引用
收藏
页码:935 / 946
页数:12
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