Ultralow Voltage FinFET- Versus TFET-Based STT-MRAM Cells for IoT Applications

被引:13
作者
Garzon, Esteban [1 ]
Lanuzza, Marco [1 ]
Taco, Ramiro [2 ]
Strangio, Sebastiano [3 ]
机构
[1] Univ Calabria, Dept Comp Engn Modeling Elect & Syst DIMES, I-87036 Arcavacata Di Rende, Italy
[2] Univ San Francisco Quito USFQ, Inst Micro & Nanoelect IMNE, Quito 170901, Ecuador
[3] Univ Pisa, Dipartimento Ingn Informaz DII, I-56122 Toscana, Italy
关键词
Tunnel-FET (TFET); ultralow voltage; double-barrier magnetic tunnel junction (DMTJ); STT-MRAM; TECHNOLOGY PLATFORM; SRAM CELL; LOW-POWER; PERFORMANCE; DESIGN; MARGIN; MOSFET; LOGIC;
D O I
10.3390/electronics10151756
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Spin-transfer torque magnetic tunnel junction (STT-MTJ) based on double-barrier magnetic tunnel junction (DMTJ) has shown promising characteristics to define low-power non-volatile memories. This, along with the combination of tunnel FET (TFET) technology, could enable the design of ultralow-power/ultralow-energy STT magnetic RAMs (STT-MRAMs) for future Internet of Things (IoT) applications. This paper presents the comparison between FinFET- and TFET-based STT-MRAM bitcells operating at ultralow voltages. Our study is performed at the bitcell level by considering a DMTJ with two reference layers and exploiting either FinFET or TFET devices as cell selectors. Although ultralow-voltage operation occurs at the expense of reduced reading voltage sensing margins, simulations results show that TFET-based solutions are more resilient to process variations and can operate at ultralow voltages (<0.5V), while showing energy savings of 50% and faster write switching of 60%.
引用
收藏
页数:11
相关论文
共 41 条
[1]   Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial [J].
Alioto, Massimo .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2012, 59 (01) :3-29
[2]  
[Anonymous], PREDICTIVE TECHNOLOG
[3]  
[Anonymous], 2017, ENABLING INTERNET TH
[4]  
[Anonymous], 2015, P INT EL DEV M DIG
[5]  
[Anonymous], 2017, P 21 INT S VDAT 2017
[6]   Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) [J].
Apalkov, Dmytro ;
Khvalkovskiy, Alexey ;
Watts, Steven ;
Nikitin, Vladimir ;
Tang, Xueti ;
Lottis, Daniel ;
Moon, Kiseok ;
Luo, Xiao ;
Chen, Eugene ;
Ong, Adrian ;
Driskill-Smith, Alexander ;
Krounbi, Mohamad .
ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 2013, 9 (02)
[7]   TFET Inverters With n-/p-Devices on the Same Technology Platform for Low-Voltage/Low-Power Applications [J].
Baravelli, Emanuele ;
Gnani, Elena ;
Gnudi, Antonio ;
Reggiani, Susanna ;
Baccarani, Giorgio .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (02) :473-478
[8]  
Bhattacharya A, 2014, 2014 INTERNATIONAL CONFERENCE ON ADVANCED COMMUNICATION CONTROL AND COMPUTING TECHNOLOGIES (ICACCCT), P435, DOI 10.1109/ICACCCT.2014.7019480
[9]   Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits [J].
Chen, Yin-Nien ;
Fan, Ming-Long ;
Hu, Vita Pi-Ho ;
Su, Pin ;
Chuang, Ching-Te .
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, 2014, 4 (04) :389-399
[10]   A hybrid III-V tunnel FET and MOSFET technology platform integrated on silicon [J].
Convertino, Clarissa ;
Zota, Cezar B. ;
Schmid, Heinz ;
Caimi, Daniele ;
Czornomaz, Lukas ;
Ionescu, Adrian M. ;
Moselund, Kirsten E. .
NATURE ELECTRONICS, 2021, 4 (02) :162-170