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- [2] Runtime 3-D Stacked Cache Management for Chip-Multiprocessors PROCEEDINGS OF THE FOURTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2013), 2013, : 68 - 72
- [4] Hetero2 3D Integration: A Scheme for Optimizing Efficiency/Cost of Chip Multiprocessors PROCEEDINGS OF THE FOURTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2013), 2013, : 1 - 7