Exploring Hybrid SRAM/MRAM L2 NUCA Stacked on 3D Chip-Multiprocessors

被引:0
作者
Lee, Seunghan [1 ]
Kang, Kyungsu [2 ]
Lung, Longpil [1 ]
Kyung, Chong-Min [1 ]
机构
[1] Korea Adv Inst Sci & Technol, SSAL, Daejeon, South Korea
[2] Samsung Elect Corp, Semicond R&D Ctr, CAE Team, Suwon, South Korea
来源
2014 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | 2014年
关键词
3D IC; hybrid cache; design-time optimization; dynamic cache management; CMPS;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Non-volatile magnetic RAM (MRAM) offers high cell density and low leakage power while suffering from long write latency and high write energy, compared with conventional SRAM. The use of hybrid memories (e.g., SRAM and MRAM together) can take advantage of the best characteristics that each technology offers. In this paper, we explore the 3D-stacked SRAM/MRAM hybrid L2 cache architecture by using a design-time optimization that determined each bank capacity and a ratio between SRAM and MRAM capacities. Also, this paper proposes a runtime cache management scheme that improves the system performance. Experimental results show that the proposed method yields, on the average, 61% performance improvement in terms of instructions per second (IPS) compared to the conventional SRAM-only L2 cache or MRAM-only L2 cache.
引用
收藏
页码:26 / 27
页数:2
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